1. Field of the Invention
The field of the invention is data processing, or, more specifically, methods and apparatuses for generating negative impedance compensation.
2. Description of Related Art
Negative impedance circuits are often used in conjunction with a main amplifier in order to cancel the parasitic load capacitance. Canceling a parasitic load capacitance limits the main amplifier bandwidth and thus provides bandwidth improvement. A simple negative impedance circuit involves two cross coupled transistors along with an impedance. The cross coupling of the two transistors creates a situation where a delta increase in voltage across the parasitic load impedance results in a delta current into the cross coupled transistors which is in the opposite sense with respect to the parasitic load impedance. The delta current flows through the impedance connected to the cross coupled transistors and “returns” back to the parasitic impedance. This creates the effect of “negative” impedance connected across the parasitic load impedance and thus cancelling/reducing the parasitic impedance.
When the negative impedance circuit is connected to the main amplifier, the negative capacitive reactance part partially cancels the positive capacitive reactance presented by the load capacitance CL. The partial cancellation is due to the presence of the negative resistance part introduced by the gm of the two cross coupled transistors. The partial cancellation has a negative impact on bandwidth.